In software defined radio an Analog-to-Digital converter (ADC) needs a speed of at least 200 MSamples/s and as much resolution as is feasible for a power budget of a few milliWatt, in order to simplify automatic gain control (AGC) and relax filtering requirements. In addition, since this ADC also needs to quantize much lower bandwidth standards, a dynamic solution is desirable.
For such high speed ADCs interleaving is widely used. In high speed interleaved ADCs the effective ADC sampling frequency is increased by operating multiple ADCs alternately. Moreover, fully dynamic interleaved ADCs are of a special interest, as their total power consumption is independent of the number of parallel channels and the speed requirements for each individual channel are relaxed. However, interleaved ADCs suffer in general from mismatches among channels, gain mismatch and bandwidth mismatch. DC offset and gain mismatch are frequency-independent and can thus easily be calibrated in the digital domain. On the other hand, bandwidth mismatch due to capacitance and resistance mismatch in each sampling network of the interleaved ADC is frequency dependent and requires complex algorithms to be calibrated digitally. Consequently, spurious tones caused by bandwidth mismatch limit the high frequency input performance of interleaved ADCs. By applying correction for bandwidth mismatches in the sampling network bandwidths these spurs can be reduced. However, bandwidth errors first need to be estimated to determine how much correction, either in the digital or the analog domain, should be applied.
Conventionally, in order to be able to observe bandwidth errors a high frequency input signal is required for generating errors due to bandwidth mismatch. In a background calibration scheme this high frequency input signal can be the signal to be quantized during normal operation. However, this requires certain assumptions about the nature of this input signal, some of which are not generally met. Additionally, applying a high frequency input requires an external signal generator, at the cost of valuable chip area and design time.
Bandwidth mismatch calibration requires a practical way to detect bandwidth mismatch. While applying a high frequency sine wave to the ADC input and observing an output spectrum obviously allows for identification of bandwidth mismatch, this detection method requires both an external stimulus and quite a lot of computation in the FFT to obtain the ADC output spectrum.
U.S. Pat. No. 8,248,282 describes an analog method for implementing a programmable bandwidth sampling network to calibrate for bandwidth mismatch. No bandwidth estimation method is however proposed.
In the paper “Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs” (P. Satarzadeh et al, IEEE TCAS-I, vol. 56, no. 9, pp. 2075-2088, September 2009) a method is proposed for detecting bandwidth mismatch errors by assuming (1) some signal content is present at the ADC input just below the Nyquist frequency, and (2) no signal content is present in a small area around DC. These conditions are not generally satisfied in communication input signals, in which oversampling typically results in very little signal content in the second half of the Nyquist band. As a result, the method of Satarzadeh is only applicable in a communications context if an explicit test signal is added to the signal to be quantized, at the cost of a power-hungry, linear summator and some ADC dynamic range.
Alternatively, the paper “Adaptive Compensation of Frequency Response Mismatches in High-Resolution Time-Interleaved ADCs using a Low-Resolution ADC and a Time-Varying Filter” (S. Saleem et al., Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) 2010, pp. 561-564) describes a background method for measuring channel gain, DC offset and timing mismatch using a low resolution reference ADC. Advantageously, this allows for mismatch calibration without interrupting the ADC operation. However, the need for an additional low resolution ADC increases area, complexity and design time.
The solutions for bandwidth mismatch detection described in both above-mentioned papers however suffer from the drawback that significant additional analog circuits are required (analog signal conditioning and a redundant reference ADC, respectively) and that a significant amount of digital calculation is needed. They are thus not applicable in a low power design.
Hence, there is a need for solutions for bandwidth mismatch in a time-interleaved A/D converter that are computationally simple and do not require additional hardware.